Signal r_CNT_50HZ : natural range 0 to c_CNT_50HZ Signal r_CNT_100HZ : natural range 0 to c_CNT_100HZ Formula is: (25 MHz / 100 Hz * 50% duty cycle) Constants to create the frequencies needed: VHDL code for the design, tutorial_led_blink.vhd:Īrchitecture rtl of tutorial_led_blink is The way that I chose to do can be found below. Spend some time thinking about how you might implement this design. It is a combinatorial piece of logic, meaning that it does not require a clock to operate. A multiplexer or mux for short is a selector that will select one of a number of inputs to propagate or pass to the output. They create what is known as a multiplexer. The switches only serve to select which output to use. Everything runs all the time! It can be challenging to understand this initially, but it is the core concept that you need to master. Even if the switches are not selecting that particular frequency, the counters are still running! This is the beauty of Hardware Design and concurrency. Their job is to keep track of the number of clock pulses seen for each of the different frequencies. This means that they are all running at the exact same time. The Enable Switch (Logic 0 = No LED Drive)įor the design there are four counter processes that run concurrently. Let’s first draw the truth table for the frequency selector: Enableįor this to work correctly there will be 4 inputs and 1 output. The FPGA will be driven by a 25 MHz oscillator.
There is an additional switch called LED_EN that needs to be ‘1’ to turn on the LED. The LED frequency will be chosen via two switches which are inputs to the FPGA. For each of the blink frequencies, the LED will be set to 50% duty cycle (it will be on half the time). However this is an extremely important step! Without proper simulation you will be forced to debug your code on hardware which can be a very difficult and time consuming endeavour.ĭesign HDL code that will blink an LED at a specified frequency of 100 Hz, 50 Hz, 10 Hz, or 1 Hz. Sometimes FPGA designers who are pressed for time will try to skip step two, the simulation of their code. This tutorial is broken up into 2 stages:īoth of these steps are crucial for successful FPGA development. The best way to find these mistakes is in a simulation environment. Despite your best efforts, there will always be mistakes in your initial design. Whenever design code is written the FPGA designer needs to ensure that it works the way that it was intended. Both VHDL and Verilog are shown, and you can choose which you want to learn first. This tutorial shows the construction of VHDL and Verilog code that blinks an LED at a specified frequency. Tutorial: Your First FPGA Program: An LED Blinker Part 1: Design of VHDL or Verilog
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